The present invention relates to an information processing unit and a bus control method therefor, and more particularly, to an information processing unit having a multiplexed bus and a bus control method therefor.
As a method for improving reliability of an information processing unit, each of the constituent elements of the information processing unit can be multiplexed and a bus for mutually connecting each of the constituent elements can also be multiplexed. A prior-art technique relating to bus multiplexing is described, for example, in the U.S. Pat. No. 4,486,826.
According to this previous patent publication, when sharing a bus with a plurality of processors and a plurality of input/output controllers for directly carrying out memory accesses (a device for exchanging signals with processors, input/output control mechanisms and other buses is hereinafter to be referred to as a "unit"), and when a plurality of units have when bus requests at the same time, priorities of these units must be determined. This system employs fixed priority bus arbitration, according to which bus a grant of a unit of the highest priority is given, and this system is characterized by its extremely simple control method.
The fixed priority bus arbitration system, however, has a problem in that when bus requests from a plurality of units become congested, the average bus waiting time increases with a result that a practical bus transfer rate is lowered for each unit which uses the bus. Further, this bus arbitration system is not suitable for systems such as a real-time processing system and an on-line transaction processing system which require that processing of a specific process should be completed within a predetermined time.